A computer system may include interconnection fabric, or a bus, for purposes of communicating data between initiating bus devices called “masters” (processor cores and direct memory access (DMA) engines, for example) and target bus devices, or “slaves” (memory devices, for example). In a typical bus operation, a master initiates a bus transfer (such as a bus transfer to read or write data) with a given slave by driving appropriate address signals onto the bus to target the slave, along with the appropriate control signals and data signals (if data is being written to the slave). The slave that is the target of the bus transfer responds by generating the appropriate signals onto the bus for such purposes as transferring data to the master; receiving data from the master; indicating an error; or signaling the master to retry the bus transfer.
The bus is a limited system resource, which typically couples a single master to a single slave at any one time. Therefore, when multiple masters concurrently contend for access to the same slave, the system typically time-multiplexes bus transfers by these masters with the slave by applying an arbitration policy.